LIBRARY ieee;
USE ieee.std_logic_1164.all;

PACKAGE components IS

	--registradores
	COMPONENT regn
		GENERIC (N : INTEGER := 8);
		PORT ( R			: IN		STD_LOGIC_VECTOR(N-1 DOWNTO 0);
			   Rin, Clock	: IN		STD_LOGIC;
			   Q			: OUT		STD_LOGIC_VECTOR(N-1 DOWNTO 0) );
	END COMPONENT;
	
	--full-adder
	COMPONENT fulladder
		PORT(Cin, x , y		: IN STD_LOGIC;
			 s,Cout			: OUT STD_LOGIC);
	END COMPONENT;
	
	--tri-state buffer
	COMPONENT trin
		GENERIC (N : INTEGER := 8);
		PORT ( X	: IN		STD_LOGIC_VECTOR(N-1 DOWNTO 0);
			   E	: IN		STD_LOGIC;
			   F	: OUT		STD_LOGIC_VECTOR(N-1 DOWNTO 0) );
	END COMPONENT;

	--unidade de controle
	COMPONENT controlunit
		PORT(	instruction 	: IN  STD_LOGIC_VECTOR(7 DOWNTO 0);
				MEM				: OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
				WB, EX     		: OUT STD_LOGIC);
	END COMPONENT;
	
	--unidade logica e aritmetica
	COMPONENT ula IS
		PORT( Op				: IN  STD_LOGIC_VECTOR(1 DOWNTO 0);
			  X, Y				: IN  STD_LOGIC_VECTOR(7 DOWNTO 0);
			  S					: OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
			  Cout				: OUT STD_LOGIC;
			  Overflow			: OUT STD_LOGIC);
	END COMPONENT;
	
	--somador de enderecos
	COMPONENT adder IS
	PORT(currAdd :IN STD_LOGIC_VECTOR (7 DOWNTO 0) ;
		 nextAdd :OUT STD_LOGIC_VECTOR (7 DOWNTO 0));
	END COMPONENT;
	
	--contador de clock de 3 bits
	COMPONENT upcount
		PORT ( Clear, Clock	: IN		STD_LOGIC;
			   Q			: BUFFER	STD_LOGIC_VECTOR(2 DOWNTO 0) );
	END COMPONENT;
	
	--unidade de memoria de instrucoes
	COMPONENT inst_mem IS
		PORT ( Address		: IN STD_LOGIC_VECTOR(7 DOWNTO 0);
			   Instruction	: OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
			   Immediate 	: OUT STD_LOGIC_VECTOR(7 DOWNTO 0));
	END COMPONENT;
	
	--unidade de registradores
	COMPONENT registers IS
		PORT (  Instr				: IN	STD_LOGIC_VECTOR(7 DOWNTO 0);
				R1, R2, R3, R4		: IN 	STD_LOGIC_VECTOR(7 DOWNTO 0);
				Imed				: IN 	STD_LOGIC_VECTOR(7 DOWNTO 0);
				R1Out, R2Out		: OUT 	STD_LOGIC_VECTOR(7 DOWNTO 0));
	END COMPONENT;
	
	--decoder de sinais pra ula
	COMPONENT ulaDecoder IS
		PORT (  Instr				: IN	STD_LOGIC_VECTOR(3 DOWNTO 0);
				Op					: OUT 	STD_LOGIC_VECTOR(1 DOWNTO 0));
	END COMPONENT;
	
	--unidade de fetch de instrucao
	COMPONENT fetch IS
		PORT (  Tick				: IN	STD_LOGIC_VECTOR(2 DOWNTO 0);
				Clock				: IN	STD_LOGIC;
				Instr				: OUT	STD_LOGIC_VECTOR(7 DOWNTO 0);
				Immed				: OUT	STD_LOGIC_VECTOR(7 DOWNTO 0));
	END COMPONENT;
	
	--unidade de decode de instrucao
	COMPONENT decode IS
		PORT (  Tick					: IN	STD_LOGIC_VECTOR(2 DOWNTO 0);
				Clock					: IN	STD_LOGIC;
				Instr, Immed, Data		: IN	STD_LOGIC_VECTOR(7 DOWNTO 0);
				R1Out, R2Out, IMOut		: OUT	STD_LOGIC_VECTOR(7 DOWNTO 0);
				Ctrl					: OUT	STD_LOGIC_VECTOR(7 DOWNTO 0));
	END COMPONENT;
	
	--unidade de memoria
	COMPONENT data_mem IS
		PORT ( Tick				  : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
			   Address, WriteData : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
			   ControlSignal	  : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
			   ReadData			  : OUT STD_LOGIC_VECTOR(7 DOWNTO 0));
	END COMPONENT;


END components;